The present invention relates to improvement in an automatic synthesizing method for logic circuits using a computer.
In accordance with recent development of refinement techniques for a semiconductor integrated circuit, a larger scale circuit design has been realized. In a refined circuit, a parasitic resistance R and a parasitic capacitance C of a line connecting circuit elements are relatively increased, so as to largely influence the circuit, and such influence has become more significant than influence of the circuit elements on the circuit.
Under such circumstances, in a conventional automatic synthesizing method for logic circuits, a virtual wiring model is used in automatic synthesis of the logic circuits. In the virtual wiring model, a length of a line is defined with regard to each group of lines having the same number of branches, for example, a group of lines having no branch, a group of lines having two branches, etc. A synthesizing tool calculates, with regard to each defined length, a capacitance, a resistance and an area of the line by multiplying the defined length by a capacitance, a resistance and an area per unit length, respectively. In the conventional synthesizing method, logic circuits are automatically synthesized by using a previously set virtual wiring model, and a mask layout is subsequently generated on the basis of a net list resulting from the automatic synthesis. Thereafter, an actual line length is extracted from the mask layout with regard to each fanout number (number of branches). Predetermined one line length is selected among the line lengths having each fanout number as a representative line length, and the virtual wiring model is modified on the basis of the representative line length. Then, logic circuits are synthesized and a mask layout is generated again by using the modified virtual wiring model, and the resultant layout is verified whether or not it satisfies a desired performance. When it does not, the aforementioned procedures are repeated. This conventional synthesizing method is described in, for example, Design Compiler Family Reference Manual/Using Floorplanners to Improve Wiring Estimation, published by Synopsys.
In the conventional synthesizing method, the mask layout is required to be generated at least once. In contrast, in another conventional automatic synthesizing method for logic circuits, a representative line length of lines having each fanout number is estimated (predicted) with no mask layout generated. This estimation of a representative line length is carried out on the basis of information obtained from a net list of objective circuits, such as numbers of cells and gates in the circuits. Such estimation is disclosed in, for example, Japanese Laid-Open Patent Publication No. 6-196561.
In a currently adopted automatic synthesizing method for logic circuits, it is necessary to design and develop an LSI having a high operation speed, or it is occasionally necessary to complete the development in a short period of time. Therefore, there are a demand for development of an LSI having a high operation speed even by taking a long development time as well as a demand for development of an LSI having a somewhat high operation speed completed in a short period of time.
In any of the aforementioned conventional synthesizing methods, however, one representative line length is defined through selection or estimation, and a virtual wiring model using the defined representative line length is used for the logic synthesis and generation of a layout. Therefore, in response to any of the aforementioned demands, the representative line length is appropriately determined through a guesswork of a designer. It is thus difficult to meet any of the two demands.